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Application of Neural Networks to Low-Level Test Case Generation

IP.com Disclosure Number: IPCOM000102243D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Dingankar, AT: AUTHOR [+2]

Abstract

A method to use Neural Networks with a view to approximate a state machine internal. From this, the low-level test case can be generated with expected results.

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Application of Neural Networks to Low-Level Test Case Generation

       A method to use Neural Networks with a view to
approximate a state machine internal.  From this, the low-level test
case can be generated with expected results.

      As each subfunction of a chip is designed, its logic must be
verified.  Test cases consist of the current states and pairs of
vectors:  the input vectors and the output vectors.  The input vector
represents all inputs to the circuit (0's and 1's).  The output
vector represents all outputs from the circuit (0's and 1's).  The
current state is a vector of 0's and 1's describing the current state
of the logic prior to applying the input vector.  The designer must
devise an input vector chosen from one of the allowable inputs.  The
designer must also choose the current state of the circuit.  As the
input vector is applied, (knowing how the logics work) the designer
predicts the output vector. This is the expected output.  This test
case is run through a simulator, which executes the real logic, to
provide the actual output. If the expected output and the actual
output differ, the designer must decide whether the wrong output was
provided or the designed logic has a bug.  Since this design
verification is only for one small portion of the chip, fetching and
executing instructions are not feasible at this time.  Since the
designer must compute the expected outputs for every new test case,
it is very time consuming. Consequently, very few test cases are
generated at this stage, prior to integration.  This makes the
testing of the integrated chip more difficult.

      Model the logics as a Backpropagation Neural Network whose
inputs and output...