Browse Prior Art Database

Space Switch Network Error-Reporting Reduction Circuit

IP.com Disclosure Number: IPCOM000102248D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 148K

Publishing Venue

IBM

Related People

Chorpenning, JS: AUTHOR

Abstract

Described is a time division multiplexed network circuit that provides three basic functions for reducing error reporting.

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This is the abbreviated version, containing approximately 50% of the total text.

Space Switch Network Error-Reporting Reduction Circuit

       Described is a time division multiplexed network circuit
that provides three basic functions for reducing error reporting.

      In order to provide a high bandwidth network with a high
throughput capability, a space switch network is used to provide up
to 16 megabytes total throughput per attached device (eight megabytes
in and eight megabytes out).  The architecture of the network
consists of a two-position space switch which interconnects to 32
devices and provides 524 megabytes of interconnect capability.  The
configuration is architecturally expandable to any number of attached
devices that the technology will support.  By using this space switch
network concept, the operational bandwidth will increase as the
number of attached devices increases.  This is unlike a typical bus
or local area network (LAN), where the bandwidth is fixed and each
device that is added reduces the total operational bandwidth that is
available to each device.

      The space switch network is a time division multiplexed
network, where a continuous loop counter cycles through each memory
position whose output is used as an address selection for a
multiplexer.  The continuous loop counter creates time slots for data
to flow from the input to the output. Architecturally, the design
provides 1,024 time slots per counter loop, or frame, 8,000 times per
second.  Utilizing a space switch controller to randomly write the
memory, any input can be assigned as a source for the output in any,
or all, time slots.

      Fig. 1 illustrates the prior-art use of a single element of the
space switch configuration.  It is typically used in the
interconnection of telephone, or similar applications, where errors
are handled by the end users.  In this configuration, the number of
potential errors that can occur is quite high.  Theoretically, every
input byte of all of the inputs could be in error for some period of
time.  Therefore, error reporting has the potential to swamp a
maintenance microprocessor function with 1,024 x 8,000 x 32 =
262,144,000 errors per second.

      In digital networking, a central maintenance microprocessor is
typically used to off-load most of the end-users networking error
reporting and to provide a central maintenance function for the
network. Therefore, the objective of the concept described herein is
to reduce the number of potential errors to a minimum and to limit
the error reporting as infrequently as possible without any loss of
system network integrity.

      The concept first reduces the number of errors by identifying
the source that is experiencing an error, rather than reporting the
error itself.  Second, it limits the error reporting, as infrequently
as possible, by limiting the error reporting once for each frame.
This provides the maintenance functions with sufficient information
to statistically identify the failing unit path and have it...