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Browse Prior Art Database

Optimum Timing Auto-Configurable Microcoded Memory Controller

IP.com Disclosure Number: IPCOM000102267D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 121K

Publishing Venue

IBM

Related People

Hardell WR, Jr: AUTHOR [+3]

Abstract

Disclosed is a means for a memory controller to automatically configure itself for the particular DRAMs that are used and the system clock speed. Because this controller is microcoded it can be easily updated for future DRAMs without changing the base controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Optimum Timing Auto-Configurable Microcoded Memory Controller

       Disclosed is a means for a memory controller to
automatically configure itself for the particular DRAMs that are used
and the system clock speed.  Because this controller is microcoded it
can be easily updated for future DRAMs without changing the base
controller.

      This method is designed for systems where it is desirable to
plug different types and/or speeds of DRAMs into one memory card.
Also, this method allows the memory card to be plugged into systems
with different clock cycle times.

      For this system to work, the controller must get a type code
for the valid types of DRAMs.  (Note:  A DRAM with a different access
time will be considered a different type.) If the DRAMs are on SIMMs,
then the type code could be part of the SIMM.  With the type code
built into the SIMMs, there would be no special jumpers for the user
to bother with. Also, the controller chip will need to know the
system cycle time.  If the controller chip receives a Refresh Request
pulse (clock) or a real time clock that is guaranteed to be the same
frequency in all systems, then the controller chip can determine the
system clock speed by counting the number of system clocks per
Refresh Request or real time clock.  If the controller can determine
the clock speed in this manner then the user will not have to bother
with jumpers for the system clock speed.

      Figure 1 shows a possible configuration f...