Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Storage Control for a Two-Configuration System Design

IP.com Disclosure Number: IPCOM000102269D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+3]

Abstract

The IBM RISC System/6000 processor chips have been designed such that two distinct system configurations can be created from the same parts. The high performance/high cost system has 4 D-Cache chips and a 16- byte memory interface (which requires pairs of memory cards). The low performance/low cost system has 2 D-Cache chips and a 8-byte memory interface (which requires only single memory cards). The two configurations are shown in Figures 1 and 2.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Storage Control for a Two-Configuration System Design

       The IBM RISC System/6000 processor chips have been
designed such that two distinct system configurations can be created
from the same parts.  The high performance/high cost system has 4
D-Cache chips and a 16- byte memory interface (which requires pairs
of memory cards).  The low performance/low cost system has 2 D-Cache
chips and a 8-byte memory interface (which requires only single
memory cards).  The two configurations are shown in Figures 1 and 2.

      This disclosure describes the method of controlling the two
different memory sub-systems with one storage control chip that has
minimal additional logic.

      The following table shows the sizes of the different memory
requests for the high performance and low cost systems.  The Storage
Control Unit (SCU) has a mode pin to tell it which system it is in.
The SCU has counters for the various memory functions.  The mode pin
is used to determine the terminal count for each function.

      The memory card addressing is also different for the two
configurations.  In a high performance system the real (byte) address
that the SCU receives is truncated to a quad word address (the lower
4 bits are dropped) before it is sent to the memory cards.  However,
in the low cost system the real (byte) address that the SCU receives
is truncated to a double word address (the lower 3 bits are dropped)
before it is sent to the memory cards.  The address c...