Browse Prior Art Database

Streamlined Status Reporting Scheme for Adapter Cards

IP.com Disclosure Number: IPCOM000102272D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 101K

Publishing Venue

IBM

Related People

Frazier, GR: AUTHOR [+2]

Abstract

The implementation described here allows a host computer to rapidly obtain command completion status for commands sent to an adapter card. It does this by allowing command completion status for multiple commands to be transferred by a single register access operation, provided that no errors have occurred in their executions. If errors occurred, however, the scheme provides a method for the host to obtain detailed error recovery information.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Streamlined Status Reporting Scheme for Adapter Cards

       The implementation described here allows a host computer
to rapidly obtain command completion status for commands sent to an
adapter card.  It does this by allowing command completion status for
multiple commands to be transferred by a single register access
operation, provided that no errors have occurred in their executions.
If errors occurred, however, the scheme provides a method for the
host to obtain detailed error recovery information.

      The register which provides the command completion status
information is called the Interrupt Status Register (ISR).  It may be
accessed by hosts of varied word widths up to the ISR width.  It
contains N+1 bits, with the first N bits indicating the completion of
one of N commands which can be stored for execution in the adapter,
and the (N+1)st bit indicating the occurrence of an error during the
execution of one of the commands which completed.  Whenever one or
more commands completes, the adapter sets the appropriate ISR bits
representing the commands which completed and also sets bit (N+1) if
errors occurred.  If bit (N+1) is set, then the host may obtain
detailed error information by reading a buffer.  If bit (N+1) is not
set, however, the host needs only to read the ISR, thereby saving the
overhead of reading the buffer.  The ISR is cleared as it is read by
the host.

      The ISR implementation requires provision for asynchronous
accesses by two different processors (i.e., the host and the adapter
processor) without loss of information. The adapter processor may set
bits at any time to indicate command completions, and the host
processor may at any time read the ISR and thereby clear bits.  Any
time the host reads the ISR, multiple command completion bits (bit
numbers 1 - N) may be on as well as the error bit (N+1).  If
the host could always read all the ISR bits in a single read
operation, then all bits of the ISR including the error bit could
simply be cleared as the host read the register. However, if the
adapter can store a large number of commands, then the ISR may
contain more bits than the host is able to read in a single
operation.  For this case, logic must be provided which ensures that
if the error bit (N+1) was turn...