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Browse Prior Art Database

Event Counter Using Few Chips

IP.com Disclosure Number: IPCOM000102277D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Nathanson, BJ: AUTHOR

Abstract

The disclosed circuit counts occurrences of various events in a system. Such a circuit might be used in a processor to monitor performance; in this case "events" could include cache misses, instruction fetches, and so on. Standard counter ICs can prove inadequate for event counting because (1) they are too small to hold large counts and (2) each event requires a separate counter. The disclosed circuit avoids these problems.

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Event Counter Using Few Chips

       The disclosed circuit counts occurrences of various
events in a system.  Such a circuit might be used in a processor to
monitor performance; in this case "events" could include cache
misses, instruction fetches, and so on.  Standard counter ICs can
prove inadequate for event counting because (1) they are too small to
hold large counts and (2) each event requires a separate counter.
The disclosed circuit avoids these problems.

      The circuit is shown in the figure.  The RAM contents are
presumed known at the start: all locations have been read previously,
or all have been zeroed.  The monitored system provides a logic high
or low on each event line to indicate the occurrence or
non-occurrence of an event.  At each sampling time, these lines are
allowed to address a RAM location; the location's contents are than
read out, incremented, and written back.  Thus the RAM location whose
binary address is 101100 will contain the number of samples during
which the first, third, and fourth event were occurring and the
second, fifth, and sixth not occurring.

      The number of event lines is determined by the number of
addresses in the RAM.  An 8K RAM has 13 address lines and so has 13
event inputs available.  The largest event count is determined by the
RAM word width.  For example, three 8-bit RAMs addressed in parallel
will accommodate counts up to 16,777,215 at each RAM address.  If
non-volatile RAM is used, counts w...