Browse Prior Art Database

Nest-Enclosed Self-Aligned Transistor

IP.com Disclosure Number: IPCOM000102293D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Desilets, BH: AUTHOR [+4]

Abstract

This article describes a method for fabricating a fully self-aligned vertical npn (or pnp) bipolar device. It employs as few as four mask levels, including collector implant, trench isolation, device and contact formation. Basically, the process makes repetitive use of a single opening to form base and emitter. Therefore, most process steps are self-aligned, and the device structure is symmetrical. The process intrinsically incorporates sidewall oxides as an integral isolation between base and collector which results in minimum junction capacitances. The process steps are listed in the following:

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Nest-Enclosed Self-Aligned Transistor

       This article describes a method for fabricating a fully
self-aligned vertical npn (or pnp) bipolar device.  It employs as few
as four mask levels, including collector implant, trench isolation,
device and contact formation. Basically, the process makes repetitive
use of a single opening to form base and emitter.  Therefore, most
process steps are self-aligned, and the device structure is
symmetrical.  The process intrinsically incorporates sidewall oxides
as an integral isolation between base and collector which results in
minimum junction capacitances. The process steps are listed in the
following:

      Fig. 1:  Use pre-patterned I/I n- pockets 10 on n+ epi 12 for
collectors (on p substrate) with trench formed to isolate the devices
(not shown).  TEOS oxide 14 / Al2O3 16 / nitride 18 / resist are
deposited on the substrate.  An opening 20 aligned to the n- pocket
is made with lithographic, dry and isotropic wet etch techniques.
The opened n- surface is thermally oxidized 22 followed by an O2 RIE
step.  To remove oxide, use the overhanging dielectric as a mask
aperture.

      Fig. 2:  A P-type MTE (medium temperature epi) film 24 is grown
into the structure to form the base and then is reoxidized 26.

      Fig. 3:  The aperture is again used to remove the oxide on top
of the intrinsic base.  An in-situ doped n+ LPCVD polysilicon 28 is
deposited to form the emitter.

      Fig. 4:  After the emi...