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Browse Prior Art Database

Stacked TAB Chip Carrier

IP.com Disclosure Number: IPCOM000102302D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Murphy, RG: AUTHOR

Abstract

Using current Tape Automated Bonding (TAB) technology, both memory and/or logic chips can be packaged together using one of several packaging methods. The first (Fig. 1) is the TAB-to-TAB method where individual TABs (with chips attached) are joined (soldered) together at the OLB lead length of the upper chip tape.

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Stacked TAB Chip Carrier

       Using current Tape Automated Bonding (TAB) technology,
both memory and/or logic chips can be packaged together using one of
several packaging methods.  The first (Fig. 1) is the TAB-to-TAB
method where individual TABs (with chips attached) are joined
(soldered) together at the OLB lead length of the upper chip tape.

      A second method is to bond the chips together (Fig. 2) and have
two different tape designs (mirror image) escape each chip separately
and common the leads at the OLB.  This is the chip-to-chip method.
Both methods would permit multi-chip TAB modules to be attached to
the surface area of only one TAB position on a printed circuit card
or other carrier.

      The number of stacked chips is not limited to two, for as many
as three or four high (possibly more) could be assembled using these
methods (Fig. 3).