Browse Prior Art Database

Method to Prevent Channel Access to Non-Reset CTCA Devices

IP.com Disclosure Number: IPCOM000102304D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Butter, AS: AUTHOR

Abstract

This invention relates to the IBM System/370 I/O Interface *. Disclosed is an alternative method by which a channel-attached Control Unit may hold off channel operations which are initiated prior to completion of the Channel System Reset function at the Control Unit. This method employs the Command-Retry procedure as opposed to the more conventional Control-Unit Busy sequence. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Method to Prevent Channel Access to Non-Reset CTCA Devices

       This invention relates to the IBM System/370 I/O
Interface *.  Disclosed is an alternative method by which a
channel-attached Control Unit may hold off channel operations which
are initiated prior to completion of the Channel System Reset
function at the Control Unit.  This method employs the Command-Retry
procedure as opposed to the more conventional Control-Unit Busy
sequence.

                            (Image Omitted)

      Hardware initiates the Channel System Reset function whenever
the channel issues the System-Reset sequence. Latch 1 in the figure
is set whenever this interface sequence is recognized by the Control
Unit.  The purpose of latch 1 is twofold.  First, it signals the
Microprocessor to reset each device within the Control Unit.
Additionally, this latch enables special command processing hardware.

      When the channel issues any non-Test I/O command to the Control
Unit while latch 1 is set, logic gate 2 enables logic block 3 to
reset the addressed device.  Additionally, logic block 3 generates
non-immediate Command-Retry status which the Control Unit presents to
the channel.  When the channel signals Accept Status or Stack Status,
logic gate 4 enables logic gate 5 to generate Device End status for
the active device.  The currently active device retains this status
for presentation to the channel following Microprocessor completion
of the Cha...