Browse Prior Art Database

Synchronous Co-Processor Support in a Virtual Memory System

IP.com Disclosure Number: IPCOM000102305D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 150K

Publishing Venue

IBM

Related People

Bowater, RJ: AUTHOR

Abstract

Disclosed is a design point for the support of co-processors in a virtual memory system, where the co-processors need to access the main processor's virtual address space and the memory management unit of the main processor is unavailable to the co-processors. A solution is provided to the problem of how to offload significant and variable amounts of adapter function, without the requirement for the adapter to become a bus master with the subsequent need of a memory management unit for virtual-to-physical translation. Background:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Synchronous Co-Processor Support in a Virtual Memory System

       Disclosed is a design point for the support of
co-processors in a virtual memory system, where the co-processors
need to access the main processor's virtual address space and the
memory management unit of the main processor is unavailable to the
co-processors.  A solution is provided to the problem of how to
offload significant and variable amounts of adapter function, without
the requirement for the adapter to become a bus master with the
subsequent need of a memory management unit for virtual-to-physical
translation.
Background:

      The distribution of workload in an advanced workstation between
the central processor (CPU) and intelligent adapters (e.g., display)
is complex with systems that use virtual memory, especially when the
virtual-to-real translation mechanism is integral with the CPU and
the connecting bus deals in physical addresses only.  Modern
microprocessors, such as the Intel i386 microprocessor, support a
virtual memory concept in which the main processor is able to access
a much larger memory address base than that of the physical memory of
the system.  Virtual memory is broken into pages of typically 4K
bytes, each of which may either be resident in physical memory or
paged out to some storage device such as a magnetic file.  Pages are
transferred between physical memory and the storage device on a
demand basis as required by the application program within the
constraints of physical memory availability.  Physical memory is
broken into slots of the same size as virtual memory pages.  Any page
may be loaded into any physical memory slot, the mapping between
virtual and physical memory being provided by a set of tables known
as the page directory and page tables.  Typically for a 32-bit
virtual address base there will be a one-page directory containing
the address of 1024-page tables, each of which contains the address
of 4096 pages, each of which contains 4K bytes.  Page directory and
tables also contain flags indicating whether the corresponding page
table or page is currently located in physical memory or is paged out
to the storage device.
Description:

      A display adapter is constructed such that it is capable of
execution functions such as clipping autonomously of the main
processor.  The adapter understands the locations within the system's
virtual memory at which its operands (bit maps, fonts, display lists,
etc.)  are located. For each operand the adapter contains a set of
registers which describe its Address (virtual in processor address
space), its Format (e.g., bits per pixel) for a bitmap and also its
Width and Height for a bitmap.  These registers will be loaded by
device driver microcode prior to an adapter operation being started.
The processor communicates with the adapter via a block of four
32-bit registers located in processor I/O address space and
implemented within the display adapter.  These registers ac...