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Method and Use Thereof for Reducing the Levels of Seed on Epoxy Laminate Surfaces

IP.com Disclosure Number: IPCOM000102306D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Bhatt, AC: AUTHOR [+6]

Abstract

Described herein is a process for reducing the levels of seed on epoxy laminate surfaces. Such surfaces require seed to initiate plating. The entire laminate is processed through a seed operation prior to circuitization, thus making it susceptible to electrical shorts between the plated conductors. Therefore, it is necessary to remove the residual seed from the laminate to prevent electrical shorts from developing. The method described here reduces seed levels below the threshold limit of 7 micro-grams/cm2 necessary for a failure to occur.

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Method and Use Thereof for Reducing the Levels of Seed on Epoxy Laminate Surfaces

       Described herein is a process for reducing the levels of
seed on epoxy laminate surfaces.  Such surfaces require seed to
initiate plating.  The entire laminate is processed through a seed
operation prior to circuitization, thus making it susceptible to
electrical shorts between the plated conductors.  Therefore, it is
necessary to remove the residual seed from the laminate to prevent
electrical shorts from developing.  The method described here reduces
seed levels below the threshold limit of 7 micro-grams/cm2 necessary
for a failure to occur.

      Prior to circuitization of internal sub-composites, the
laminate is seeded with a palladium/tin-based solution in order to
initiate copper plating.  This is accomplished by immersing the
sub-composite into the seed solution, thereby depositing a uniform
layer of seed over the entire laminate surface.  Photoresist is then
applied to the sub-composite, upon which the circuit patterns are
exposed and developed out.  The circuit line channels are then
additively plated with copper, and photoresist subsequently removed
from the surface leaving behind the circuitized laminate.

      The residual seed remaining on the epoxy laminate surface is
often the source of electrical leakage between the conductors.  Thus,
post strip processes which reduce the levels of residual seed below
the threshold limit necessary for electrical fa...