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Quick VLSI CMOS Power Estimator

IP.com Disclosure Number: IPCOM000102333D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 109K

Publishing Venue

IBM

Related People

Kugel, L: AUTHOR [+2]

Abstract

Power estimation today tends to be based upon measurement in a simulated chip environment, or a rough estimation based upon number of circuits.

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This is the abbreviated version, containing approximately 52% of the total text.

Quick VLSI CMOS Power Estimator

       Power estimation today tends to be based upon measurement
in a simulated chip environment, or a rough estimation based upon
number of circuits.

      The advantage of this algorithm is that chip power and thus
system-cooling requirements of small computers could be estimated
early in the product cycle.

      This algorithm estimates chip power from a VLSI chip schematic
consisting of macros interconnected by buses. Each macro is assigned
an average switching energy per output net (Es) and a probability of
a macro output net switching/input transition (Ps).  Ps might be a
single number or a distribution correlated with other distributions,
such as Ps for other macros.

      USE IN TOP-DOWN SYSTEM DESIGN

      This algorithm is oriented toward use in an interactive
top-down design system.  The algorithm takes advantage of statistical
tuning, by adjusting chip power to account for logic structure, logic
levels, number of buses, bus widths, macro widths, multiple clocks,
unclocked latches, different switching characteristics of different
macros and statistical variations in chip fabrication and in chip
operation.  In top-down design the system is designed in a
hierarchical fashion, starting with the highest level schematic, then
detailing the schematic.  This is followed by board and cable
physical design, frames and covers, and then chip physical design.

      The recommended time to use this algorithm is during board
physical design, after the chip placement, as the driver switching
energy is dependent upon driver output capacitance.  Manhattan
distance of off- chip nets could be used to estimate driver
capacitance.

      ALGORITHM

      (FORTRAN nomenclature will be used where appropriate to define
the equations, and k denotes bit number k, where k = 1,2, ...,n.)
1.   Ps(k,j)i) = mean probability of a macro output net (within
output bus k) switching if there is an input transition to macro j or
if there is a latch enable pulse.
2.   Es(k,j) = When a macro output net (within output bus k)
switches, Es is the average switching energy per output net.
3.   Nb(k) = number of input buses for macro k
4.   N(j) = the number of nets in bus j
5.   Nl(k) = the mean number of logic levels for macro k
6.   L(k) = the logic level at the output of macro k.
7.   F(k) = The switching frequency of latch-oriented macro k, which
is the clock frequency for clocked logic or an engineering estimation
for unlatched logic.
8.   fmax = the maximum switching frequency in the chip. All
switching activity / cycle estimation is based upon fmax.
9.   Tin(j,k) = mean number of switching transitions per fmax cycle
of a net in the bus j input to macro k.
10.  Tout (j,k) = mean number of switching transitions per fmax cycle
of a net in the bus j output from macro k.
11.  W(k) = average power generated by macro k.

      The simplest form of the algorithm is to:
1.   St...