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Technique for Reducing Active Power in Partial-Good DRAM C

IP.com Disclosure Number: IPCOM000102337D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 108K

Publishing Venue

IBM

Related People

Hovis, WP: AUTHOR

Abstract

A method for reducing the active power of partial-good DRAM components is disclosed. This technique utilizes fuse information to disable array set and restore logic in the non-operative quarter or half-chip segments, thus reducing the overall active power. This technique is applicable to both planar partial-good components as well as stacked all-good equivalent components (by address or I/O).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Technique for Reducing Active Power in Partial-Good DRAM C

       A method for reducing the active power of partial-good
DRAM components is disclosed.  This technique utilizes fuse
information to disable array set and restore logic in the
non-operative quarter or half-chip segments, thus reducing the
overall active power.  This technique is applicable to both planar
partial-good components as well as stacked all-good equivalent
components (by address or I/O).

      This technique, which will allow for an active power reduction
for a partial-good by I/O stacked all-good equivalent component, is
to use fuse information to disable array set and restore logic in the
unused I/Os.  This technique is also valid to reduce the active power
of planar partial-good components (see Fig. 1).  Only 1 fuse per I/O
is required with the resultant output being ANDed with the array set
or enable of the I/O quadrant.  For this technique to be viable, the
component must have separate control logic or drivers for each
quadrant.  Also, the subsequent back-end CE timings must still
operate with the unused quadrants disabled. Array power in DRAM
components is growing as twice as many bits, and hence bit lines, are
set with each new generation. An example of the power savings is
given below, with the following equation used to determine the array
power.
   P = I*V where I = C*DV/DT or I= C*(delta V)/(Delta T)
P = power           or P = C*V*V/T
I = current
V = voltage
C = capacitance
DV = Delta voltage
DT = Delta time

      As an example, assume a 16 Mb DRAM (with 4 I/Os) which has 2048
bits activated per I/O (11/11 RE/CE addressing). Assume additionally
that each bit line has 422 fF of total capacitance (cell and bit
line) and that the array voltage is 3.3 V typically.  Since bit lines
are usually folded, with 2 used to sense each bit, then 2048 bit
lines are set to ground each cycle (assume, for the sake of argument,
from VDD for simplicity), and the other 2048 or the pair remain at
VDD.  This results in (2048 bit lines X 422 fF / bit line X 4
quadrants / chip) = 3.46 nF of capacitance set and restored each
cycle per component.  Let us further assume that this occurs once
every 100 nanoseconds (ns).  The...