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Reduced Self-Test Recreate Diagnostic Time Through Checkpoints

IP.com Disclosure Number: IPCOM000102339D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

Douskey, SM: AUTHOR [+3]

Abstract

Single chip isolation in self test, when multiple chips feed the signature collector (Multiple Input Signature Register - MISR), is achieved by rerunning the entire test on each chip individually and comparing the results against known good values for those chips until one or more are detected as bad. If this is done as a normal part of IPL and the system is not coming down (the test may be in non-vital logic), this could add significantly to the IPL time. Shortening rather than eliminating the diagnostics in the IPL path would be the preferred solution.

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Reduced Self-Test Recreate Diagnostic Time Through Checkpoints

       Single chip isolation in self test, when multiple chips
feed the signature collector (Multiple Input Signature Register -
MISR), is achieved by rerunning the entire test on each chip
individually and comparing the results against known good values for
those chips until one or more are detected as bad.  If this is done
as a normal part of IPL and the system is not coming down (the test
may be in non-vital logic), this could add significantly to the IPL
time.  Shortening rather than eliminating the diagnostics in the IPL
path would be the preferred solution.

      Since we are only interested in isolating the failing chip, not
completely testing the good one, why not run just the failing
pattern?  That is the basis of the solution described here.

      A checkpoint scheme will be implemented to reduce the
diagnostic time.  Rather than comparing the signature in the MISR at
the end of the total test, it is compared many times throughout the
test.  This allows reduction of failure diagnostics in two ways.
First, most failures will fall out well before the total test time
has elapsed, and second, only the failing pattern needs to be
retested against each chip.

      The figure illustrates, on the left, the good machine path with
multiple signature compares, and on the right, the recreate
diagnostic path implemented.  Note that the SEED references represent
the value in the Pseudo-Random Pattern Generator (PRPG), while SIGs
are in the MISR.  Also note that the '*' indicates data loaded, '#'
data read and compared, and all data not marked by either of these
symbols is generated during the test.

      In the good machine path, SEED0 and SIG0 are the only data
loaded.  All the following PRPG Seeds and MISR Signatures are created
by hardware during the test.  All MISR values must be predicted and
stored for compares at all checkpoints.  The data volume will
increase based on the number of checkpoints chosen.  Comparing the
MISR 50 times over a 20-second test greatly decreases the time it
takes to detect the average failing card.  Within the first pattern,
0.4 second, more than half of the logic is tested.  Thus, the average
time to failure detect has been dropped...