Browse Prior Art Database

Gate Level Stack to Minimize Contact-Spacing Groundrule

IP.com Disclosure Number: IPCOM000102349D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Sheets, JE: AUTHOR [+2]

Abstract

Described is a method which allows a significant density improvement in integrated circuits by reducing the minimum acceptable spacing between the gate level conductor and contacts to the adjacent diffusions. The physical spacing required between the gate of a transistor and the contact holes to the source and drain on either side of the gate is often the dominate impediment to enhanced density (i.e., more transistors per unit area) on integrated circuits. This method allows a significant reduction in the minimum acceptable space between the gate and source/drain contacts by enhancing the dielectric between the transistor terminals.

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Gate Level Stack to Minimize Contact-Spacing Groundrule

       Described is a method which allows a significant density
improvement in integrated circuits by reducing the minimum acceptable
spacing between the gate level conductor and contacts to the adjacent
diffusions.  The physical spacing required between the gate of a
transistor and the contact holes to the source and drain on either
side of the gate is often the dominate impediment to enhanced density
(i.e., more transistors per unit area) on integrated circuits. This
method allows a significant reduction in the minimum acceptable space
between the gate and source/drain contacts by enhancing the
dielectric between the transistor terminals.

      A gate level conductor (typically, polysilicon) is capped with
a relatively thin dielectric of type A (typically, silicon nitride)
before gate level patterning. After the gate layer is patterned by
established means, one is left with an insulating film over the gate
conductor (see Fig. 1).  After subsequent processing to define the
transistor source and drain diffusion areas using this same type A
dielectric, a relatively thick dielectric of type B (typically,
silicon dioxide) is deposited on the wafer surface.  This film is
typically reflowed to smooth topology for subsequent conductor layers
(see Fig. 2).  Notice that the gate conductor is now totally
encapsulated in the type B dielectric.

      Conventional reactive ion etch (RIE) contact-etching techniqu...