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Browse Prior Art Database

Concurrent CRT/PDP Display With FIFO and Frame Buffer

IP.com Disclosure Number: IPCOM000102361D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 101K

Publishing Venue

IBM

Related People

Amagami, A: AUTHOR

Abstract

Disclosed is a display subsystem for driving both a Cathode Ray Tube (CRT) monitor and a Plasma Display Panel (PDP). The display control signals such as dot clock, horizontal sync, vertical sync, etc., required for driving the CRT are not the same as the display control signals required for driving the PDP. This invention is widely applicable for any display devices which have similar interface signals.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Concurrent CRT/PDP Display With FIFO and Frame Buffer

       Disclosed is a display subsystem for driving both a
Cathode Ray Tube (CRT) monitor and a Plasma Display Panel (PDP). The
display control signals such as dot clock, horizontal sync, vertical
sync, etc., required for driving the CRT are not the same as the
display control signals required for driving the PDP.  This invention
is widely applicable for any display devices which have similar
interface signals.

      The figure shows the functional blocks comprising of two
sections: section A and section B.  Section A operates in accordance
with the CRT clock, and section B operates in accordance with the PDP
clock.  The frequencies of these clocks do not have to be identical.
In this system the CRT clock is selectable from plural predetermined
values in accordance with the display mode selected by the operator
or application software.  On the other hand, the PDP clock has a
fixed frequency so that it can generate constant timing to access the
screen buffer 5 and to control the PDP.  For example, the frequency
of the PDP clock is selected to be no less than the frequency of the
CRT clock.

      A serial-to-parallel register 2 converts the serialized video
data to parallel data having the necessary bit width for screen
buffer 5.  A frame detection circuit 2 detects the position where the
video data is to be displayed on the CRT screen and generates a
screen buffer address according to the position of the pixel on the
CRT screen.  This circuit is applicable for both an interlace display
mode and non-interlace display mode.

      A FIFO 3 receives the screen data and screen address to be
stored.  The FIF...