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Prioritizing Factor for Nets in Timing-Based Physical Design of VLSI Chips

IP.com Disclosure Number: IPCOM000102363D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 140K

Publishing Venue

IBM

Related People

Hauge, PS: AUTHOR [+3]

Abstract

During physical design (PD) of very large-scale integrated (VLSI) chips, as circuits are placed and connecting wires are routed, attention must be paid to the lengths of individual wires, in order to insure that signals will arrive at their destinations within specified time intervals (timing constraints will be met). The problem of maintaining timing closure during PD increases as chips become large and complex. Computer programs which automatically perform physical layout of chips (PD tools) can utilize information for timing guidance efficiently if that information is net-specific: that is, if the information pertains to individual nets, rather than to complicated paths through the design.

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Prioritizing Factor for Nets in Timing-Based Physical Design of VLSI Chips

       During physical design (PD) of very large-scale
integrated (VLSI) chips, as circuits are placed and connecting wires
are routed, attention must be paid to the lengths of individual
wires, in order to insure that signals will arrive at their
destinations within specified time intervals (timing constraints will
be met).  The problem of maintaining timing closure during PD
increases as chips become large and complex.  Computer programs which
automatically perform physical layout of chips (PD tools) can utilize
information for timing guidance efficiently if that information is
net-specific: that is, if the information pertains to individual
nets, rather than to complicated paths through the design.

      Previous work provides a means of determining limits on the
length of each net such that if the wires conform to these limits
then timing constraints will be met.  This work led to the
development of the IMPACT timing-driven design tool.  In practice,
however, not every wire length limit is met.  Therefore, it is vital
to prioritize the nets so that greater effort will be made by a PD
tool to manage the lengths of those wires which will more adversely
affect the signal arrival times if their limits are exceeded.

      This article describes such a means of prioritizing the nets in
a timing-driven PD environment.  The method has been implemented
within IMPACT and has been demonstrated to improve significantly the
timing characteristics of a design over the results of using IMPACT
without net prioritization. The method may also be used by other
tools: it is not limited to use with IMPACT.  Priority for nets
meeting their length limit is conveyed through a Net Importance
Factor, or NIF.  It is important to understand the role that NIF
plays in timing-based PD.  NIF is not simply a measure of the
criticality of a net: a net having a small NIF value may lie on a
more timing-critical path than a net having a large NIF value.  Nor
is NIF a second-order modification of the timing influence.  When a
PD tool makes a decision, for example, where to place a circuit, it
will look at the lengths of the wires that connect to it.  If these
wires lie on a critical path, their lengths will have short upper
limits (given by IMPACT, or similar tool).  When there are many
critical paths competing for short connections, however, it is rare
that all length limits will be observed.  Therefore, it is necessary
to provide guidance to the PD tool as to the relative timing
consequences of a limit being exceeded.  NIF provides this guidance
as a multiplicative factor in the cost function for violating a
length limit.  In this regard, NIF is distinct from, but possesses
comparable significant to, the net criticality measure, as given by
the length limit.  Put another way: the length limits provide a
many-dimensional target area for the PD tool to hit.  The NIF v...