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Limiting the Short-Circuit Current in Defective Integrated Decoupling Capacitors

IP.com Disclosure Number: IPCOM000102382D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+3]

Abstract

This articles describes methods of preventing an integrated defective decoupling capacitor from causing a breakdown of the entire chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Limiting the Short-Circuit Current in Defective Integrated Decoupling Capacitors

       This articles describes methods of preventing an
integrated defective decoupling capacitor from causing a breakdown of
the entire chip.

      The decoupling capacitors in a CMOS chip are positioned on top
of a p-conductive region, utilizing the thin gate oxide as a
dielectric.  The capacitor plate connected to voltage supply VDD is a
polysilicon layer.  The counterplate is the inversion zone below the
thin oxide.  It electrically contacts the n-conductive region at the
edge of the capacitor, where it is connected to ground GND.  If the
capacitor contains a defect in the gate oxide, current flows from VDD
both to the n-region and the p-conductive substrate.

      To prevent the short-circuit current from causing a breakdown
of the entire chip, it may be limited or the capacitor may be
switched off.

      For limiting the current, Fig. 1 shows a resistor which is
directly built into the VDD lead.  As shown in Fig. 2, it is also
possible to use a p-FET, having its gate connected to GND, in lieu of
the resistor.  As a result, the transistor is switched on in full,
and the magnitude of the internal resistance is determined by the
channel length and the channel width.

      Another method is shown in Fig. 3 providing for the current to
GND to be limited by an n-FET.  The great advantage of such an
n-channel transistor is that it is readily intregratable with the
decoupling capacitor.

      In Fig. 4, the decoupling capacitor is arranged in a CMOS chip
above the n-type well.  The dielectric of the capacitor is the thin
gate oxide.  The upper capacitor plate consists of the gate
polysilicon layer and the bottom plate of the conductive in...