Browse Prior Art Database

In Situ Process for Planarizing Layers

IP.com Disclosure Number: IPCOM000102384D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Hoerner, E: AUTHOR [+2]

Abstract

This article describes a process for in situ planarizing layers in semiconductor technology.

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This is the abbreviated version, containing approximately 100% of the total text.

In Situ Process for Planarizing Layers

       This article describes a process for in situ planarizing
layers in semiconductor technology.

      The figure shows substrate 1 with the overlying metallization
M.  In addition, substrate 1 is coated with a layer 2, whose
thickness is noticeably above the desired value.  Layer 2 is coated
with photoresist 3 which is exposed and developed using the mask
required for structuring.

      In the RIE step, the etch rate is chosen such that the resist
on metallization M is removed along with part of layer 2 to achieve
the desired thickness and to simultaneously structure layer 2.

      The described process facilitates the planarization of layers,
thus saving time and material, as one coating and one RIE step are
eliminated for each metal layer.  A further advantage is that the
precision and the process yield are increased.  As the RIE step
permits an accurate determination of the endpoint, the process
control for planarization is simplified.