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Edge Cost Optimization for Chip Wiring

IP.com Disclosure Number: IPCOM000102388D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Knigge, B: AUTHOR [+4]

Abstract

Maze runner-type routers are used for most VLSI wiring applications. The edge costs (control parameters) employed for those routers have a great influence on the wiring results. It is shown that particular edge cost equations have to be complied with.

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Edge Cost Optimization for Chip Wiring

       Maze runner-type routers are used for most VLSI wiring
applications.  The edge costs (control parameters) employed for those
routers have a great influence on the wiring results.  It is shown
that particular edge cost equations have to be complied with.

      The new edge costs applied to a maze runner router considerably
decrease the via count and reduce the number of overflows to zero.

      There are two main reasons for the proposed edge costs:
      1.   To avoid local congestion For this purpose, the via and
wrong way wiring costs are augmented.  The router then prefers a
slightly longer wiring distance to a large number of vias and wrong
way wiring which usually occur in regions with a high pin density.
High via costs considerably decrease the via count.
      2.   1-channel jogs should always be wired in a single layer to
avoid blocking an extra channel in one layer without freeing a
channel in the other, and using two extra vias.  For technologies
with equal wiring capacitances in both directions, 2- channel jogs
should use both layers.  This decreases the via count and the number
of wiring channels and thus leads to increased wirability.
           Suppose an edge pointing in the preferred direction in
each layer has costs of 1, wrong way wiring a > 0 and vias b
> 0.  As maze runner routers guarantee minimum two-point connection
for given edge costs, this implies
      ...