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Wordline Sampling Technique for High Speed Cmos Drams

IP.com Disclosure Number: IPCOM000102390D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Katayama, Y: AUTHOR [+3]

Abstract

This article describes a circuit and effective layout concept for detecting the word-line transition of high speed CMOS DRAMs, having a cascade connection of PMOS and NMOS transistors with single NMOS pull- down and PMOS pull-up device, respectively, to achieve the fast detection of word-line transition. The circuit can detect the word-line transition fast enough so that the sense amplifier can be triggered from the output from this circuitry.

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Wordline Sampling Technique for High Speed Cmos Drams

       This article describes a circuit and effective layout
concept for detecting the word-line transition of high speed CMOS
DRAMs, having a cascade connection of PMOS and NMOS transistors with
single NMOS pull- down and PMOS pull-up device, respectively, to
achieve the fast detection of word-line transition.  The circuit can
detect the word-line transition fast enough so that the sense
amplifier can be triggered from the output from this circuitry.

      The figure illustrates the new word-line sampling technique.
Two stages of wired-OR logic quickly detect the transition of one
word-line out of many while using only small devices. A single NMOS
pull-down device TA is used for the first stage and a single PMOS
pull-up device TB is used for the second stage to reset the state.
The gate of the pull-down and pull-up devices are controlled by
feedback from the output state. We assume a PMOS transfer device for
the array for the explanation. However, the argument can be applied
to the NMOS transfer device case by using the opposite MOS device in
every case.

      The circuit operation is as follows. All of the word-lines are
high in stand-by for the PMOS transfer device case. All the wired-OR
connected PMOSs, TWL, are off, and the output is low due to the pull-
down device TA. The next stage is quite similar. All the NMOSs are
off and the output is high due to the pull-up PMOS devices TB. When
one of the wo...