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Browse Prior Art Database

Flexible Approach to Finite State Machines

IP.com Disclosure Number: IPCOM000102394D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 5 page(s) / 115K

Publishing Venue

IBM

Related People

Haess, J: AUTHOR [+4]

Abstract

The approach described in this article effectively isolates the state transition and the output function from the state coding of finite state machines (FSMs). The state transition and the output generation block are independent of state coding. If a change in state coding is required, only the state decoding and encoding logic means is affected.

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This is the abbreviated version, containing approximately 52% of the total text.

Flexible Approach to Finite State Machines

       The approach described in this article effectively
isolates the state transition and the output function from the state
coding of finite state machines (FSMs).  The state transition and the
output generation block are independent of state coding.  If a change
in state coding is required, only the state decoding and encoding
logic means is affected.

      Flow charts or similar representations (Fig. 1) are normally
used to develop the control logic of a VLSI chip. Such
representations allow a well-structured and systematic description of
the control logic.

      For hardware mapping such description, the concept of FSMs is
used.  FSMs consist of a state register and combinational logic means
(Fig. 2).  Unfortunately, the state coding of FSMs is linked to their
logical behavior. If the designer is forced to experiment with
different state codings because of speed or area constraints, the
complete combinational logic means has to be changed.

      To avoid this, a flexible approach has been chosen which allows
a more flexible implementation of FSMs and which may be physically
realized or used as a syntactical element in a register transfer
language.

      The proposed approach comprises the following elements:
      o    A state register
           This register contains the current state.  In response to
each clock, the next state is loaded into the state register.
      o    A state decode means This logic means is fed with s state
variables of the state registers, generating a state decode signal
for each state of the FSMs.  For n states, n decodes are generated.
      o    A state transition block This logic means generates the
logical conditions for the next state to go to from the i inputs and
the n state decodes.
      o    A sta...