Browse Prior Art Database

Improvements to Display Identification

IP.com Disclosure Number: IPCOM000102395D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 124K

Publishing Venue

IBM

Related People

Canton, DA: AUTHOR [+3]

Abstract

This article relates to microcomputer display systems and in particular to improvements in the interface between a visual display unit and a microcomputer display adapter.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Improvements to Display Identification

       This article relates to microcomputer display systems and
in particular to improvements in the interface between a visual
display unit and a microcomputer display adapter.

      A first improvement, which provides the interface with an open
identification architecture, will now be described. Specifically, the
open architecture is operable for multiplexing fifteen bits onto the
conventional three identification (ID) lines.

      An example of a microcomputer display system of the prior art
can be produced by coupling one of the range of IBM PS/2* displays
(such as the 8514 color display) to an IBM PS/2 system unit (such as
the IBM PS/2 model 80).  The interface between the PS/2 display and
the PS/2 system unit provides three ID bits from which the display
adapter in the system unit determines which PS/2 display is attached.
The number of different displays that can be indentified by the
adapter is therefore limited.  Furthermore this interface provides no
facility for passing image size data between the display and the
adapter to enable pixel pitch to be calculated in accordance with
image scaling.

      The open architecture overcomes these limitations by providing
an interface with the potential for extending the available ID bits
and for transferring image size data between the display adapter and
the display.  This interface requires no logic changes to the display
adapter and is fully compatible with the current range of PS/2
displays.
Description

      The adapter is provided with logic for transmitting mode
information to the display over the lines carrying synchronization
(sync) signals to the display.  The mode information is transmitted
by setting the horizontal and vertical sync polarities to one of five
available configurations (four polarity combinations and no syncs).
The display comprises a multiplexer for selecting the three ID bits
returned to the adapter.  The multiplexer is controlled by the "mode"
information decoded from the syncs. The display can therefore
transmit five sets of three bits of data (fifteen bits in all) back
to the adapter.  The input to the multiplexer is hard-wired to
represent the following data:

      VERTICAL IMAGE SIZE (in default mode).  A range from
(typically) 100 mm to 500 mm is available.  Increments are chosen so
that the ratio of increment to image size is constant.  Five bits are
allocated.

      HORIZONTAL IMAGE SIZE (in default mode).  A range from
(typically) 150 mm to 500 mm is available.  Increments are chosen so
that the ratio of increment to image size is constant.  Five bits are
allocated.

      PIXEL AND TIMING FORMAT (in default mode).  A range compatible
with the Video Graphics Adapter (VGA) standard is provided.  Four
bits are allocated.

      PARITY.  One bit is allocated.

      By sequencing the display through five modes...