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Control Circuitry for Synchronizing Digital Signals

IP.com Disclosure Number: IPCOM000102400D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Pfeifer, R: AUTHOR [+5]

Abstract

In complex digital systems, such as data processing systems, the operations to be performed are handled by a plurality of individual component groups (chips) in a parallel mode. This necessitates that the component groups operate at a synchronous clock and that the signals determining that clock be subject to as little skew as possible. The described circuit provides the necessary control function. Its operation is based on the characteristics of an unterminated transmission line.

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Control Circuitry for Synchronizing Digital Signals

       In complex digital systems, such as data processing
systems, the operations to be performed are handled by a plurality of
individual component groups (chips) in a parallel mode. This
necessitates that the component groups operate at a synchronous clock
and that the signals determining that clock be subject to as little
skew as possible.  The described circuit provides the necessary
control function. Its operation is based on the characteristics of an
unterminated transmission line.

      Signal waveforms in an environment as described below may be
sensed electronically to measure the distance to the open line end.
The measured delay is used to tune either a special receiver circuit
or the line driver such that the effect of the delay for receiving
nodes is compensated for.

      Fig. 1 shows a principal configuration of a transmission line
with no termination at the far receiving end and a termination at the
driver end.

      The main waveforms occurring in that configuration are shown in
Fig. 2.  The time interval between levels V and 2V can be measured.
It is twice as long as the line delay between the point being
monitored and the line end. Circuitry for adjusting the time interval
by the desired delay may be provided, so that a defined timing
relation of the signals is achieved without adjusting the line
length.
Example 1 - Electronic adjustment of clock signals at the driver

      Clo...