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Browse Prior Art Database

Parallel Method for Verifying the Correctness of Shift Register Chains In LSSD Designs

IP.com Disclosure Number: IPCOM000102401D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Troidl, AJ: AUTHOR

Abstract

This article discloses a method for identifying shift register chains in level-sensitive scan design (LSSD) circuitry and verifying their functional correctness. A tracing procedure is used to order all the chains on the circuit. With the ordered chains identified, all chains can be shifted in parallel to verify functional operation. This parallel shifting makes for decreased run-time over the previous method of serially shifting values through each scan chain individually.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parallel Method for Verifying the Correctness of Shift Register Chains In LSSD Designs

       This article discloses a method for identifying shift
register chains in level-sensitive scan design (LSSD) circuitry and
verifying their functional correctness.  A tracing procedure is used
to order all the chains on the circuit.  With the ordered chains
identified, all chains can be shifted in parallel to verify
functional operation.  This parallel shifting makes for decreased
run-time over the previous method of serially shifting values through
each scan chain individually.

      The shift register chain is the backbone of any circuit
designed using the rules of LSSD and containing memory element
latches.  All latches must be implemented as part of a Shift Register
Latch (SRL).  Furthermore, all SRLs must be interconnected to form
one or more shift registers, and it must be possible to shift all
shift registers in parallel. The ability to shift all registers in
parallel allows multiple tests to be applied to different networks on
the same package simultaneously.  The net effect is that test data
volume is reduced, as is the time spent on the tester.

      The shift register test verifies that the chains are properly
constructed and function properly.  That is, all SRLs can latch
values and all chains can be shifted in parallel.

      The shift register chains are processed in two steps. The first
step uses tracing algorithms, which run faster than simulating values
through the entire circuit, to verify the structural correctness of
each chain.  The second step verifies the functional operation of
each chain, as well as that of each latch in the chain, by the
parallel shifting of a value through all chains simultaneously.  In
this way fewer...