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Uncorrectable Error Flag for On-Chip Error Correction Code Systems

IP.com Disclosure Number: IPCOM000102410D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Fifield, JA: AUTHOR [+3]

Abstract

By means of a new on-chip circuit, a flag signal is generated to provide indication of an uncorrectable error when more than one error exists in a chip having on-chip error correction code (ECC). The circuit uses a segmented single error detect line for maximum circuit density.

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This is the abbreviated version, containing approximately 100% of the total text.

Uncorrectable Error Flag for On-Chip Error Correction Code Systems

       By means of a new on-chip circuit, a flag signal is
generated to provide indication of an uncorrectable error when more
than one error exists in a chip having on-chip error correction code
(ECC).  The circuit uses a segmented single error detect line for
maximum circuit density.

      Referring to the figure, an n-bit True/Complement syndrome bus
2 spans across on-chip error position calculator 4 which contains NOR
gates 6, 8, 10, and 12.  OR device 14 is an n-input OR device with
inputs connected to the n TRUE syndrome lines within bus 2.  Thus,
line 16 goes high for any error condition on bus 2.  One of N-type
transistors 18, 20, 22 or 24 pulls a single error detect line 26 or
28 low in the event of a single error.  Line 30 is driven low by
OR gate 32 when a single error occurs.  AND gate 34 generates a one,
the uncorrectable error flag, at UE when more than a single error
occurs.  P-type restore devices 36 and 38 reset lines 26 and 28 at
the end of a cycle.