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Error Correction Circuit Testing Using an On-Chip Register

IP.com Disclosure Number: IPCOM000102418D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Barth, JE: AUTHOR [+2]

Abstract

On-chip syndrome generators usually comprised of Exclusive OR (XOR) error correction circuits (ECC) may be tested using an added, on-chip register instead of tested good main memory cells to store a test vector input and resulting syndrome output. Thus, need for extensive main memory testing prior to ECC tests is avoided and faster ECC testing is achieved due to short cycle time of a small register.

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Error Correction Circuit Testing Using an On-Chip Register

       On-chip syndrome generators usually comprised of
Exclusive OR (XOR) error correction circuits (ECC) may be tested
using an added, on-chip register instead of tested good main memory
cells to store a test vector input and resulting syndrome output.
Thus, need for extensive main memory testing prior to ECC tests is
avoided and faster ECC testing is achieved due to short cycle time of
a small register.

      Referring to the figure, ECC syndrome logic 2 normally serves
memory system 4.  To test ECC 2, a test vector is loaded into static
random-access memory (SRAM) register 6 via input/output (I/O)
circuitry 8.  Write data Wd and write check bit Wc signals to
appropriate inverters within inverter block 10 drive the test vector
into ECC 2, generating intermediate syndrome outputs.  When the
syndromes are ready, signal Wc ends and read syndrome signal Rs
drives syndrome outputs from ECC 2 into check bit locations within
register 6 via appropriate inverters within block 10.  Output
syndromes are then ready to be compared with expected data.

      This system for testing ECC syndrome logic is especially useful
in early stages of production of large-scale memory chips wherein
small registers constructed to have high yield are used to test ECC
circuit on chips having relatively low yield within the main memory.