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Browse Prior Art Database

Single Error Detect Flag for Efficient Stress Testing

IP.com Disclosure Number: IPCOM000102420D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 28K

Publishing Venue

IBM

Related People

Douse, DE: AUTHOR [+3]

Abstract

A circuit technique is provided to keep track of increases in single cell fails before and after burn-in testing of chips having on-chip error correction code (ECC).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Single Error Detect Flag for Efficient Stress Testing

       A circuit technique is provided to keep track of
increases in single cell fails before and after burn-in testing of
chips having on-chip error correction code (ECC).

      Referring to the figure, n-bit error position calculator 2 is
connected to syndrome bus 4 and generates an error flag on one of
lines E1 - En in the event of a single error.  Latch 6 holds this
error state coming out of OR gate 8 for an entire cycle.  Chip
input/output (I/O) control 10 outputs the state of error latch 6 to
I/O pad 12 by proper selection of an address on bus 14.