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Browse Prior Art Database

Fast Carry Save Adder

IP.com Disclosure Number: IPCOM000102429D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Beraud, JP: AUTHOR

Abstract

Disclosed is a device which accelerates the propagation delay of a N-bit adder. It is made by a modification of the well known "CARRY SAVE ADDER" technique. The proposition saves one logic delay propagation each two stages of "CARRY SAVE ADDER".

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Fast Carry Save Adder

       Disclosed is a device which accelerates the propagation
delay of a N-bit adder. It is made by a modification of the well
known "CARRY SAVE ADDER" technique. The proposition saves one logic
delay propagation each two stages of "CARRY SAVE ADDER".

      The Conventional Carry Save Adder is based on the general
concept of computing in parallel an addition with the carry input C
at 0 (zero) and another addition with carry input C at 1 (one). The
choice of the result is made at the end of computation as a function
of the real input carry values through multiplexers (MPX) (see Fig.
1).

      The proposition described herewith is a modification of the
Carry Save Adder technique to speed up the addition. Multiplexers MPX
of the second stage are combined to reduce the path of the CARRY-IN
by one multiplexer delay (see Fig. 2).
Example using 2-bit adders

      Let us consider the basic 2-bit adder made with 2 logic levels.

      In Fig. 3 a 10-bit adder is implemented in both ways normal
carry-saved-adder and modified carry-saved-adder. The first adder
stage is identical in both implementations because at the beginning
the DATA delay path is longer than the CARRY-IN delay path, so there
is no advantage to start with the modified adder. The table
summarizing logic levels shows the gain carried out by using this
proposal (see Fig. 3).

      Note that many combinations of this technique can be used with
other adder arrangements,...