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Fir Filter for Processing Sigma-Delta Modulator Outputs

IP.com Disclosure Number: IPCOM000102433D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 141K

Publishing Venue

IBM

Related People

Knox, LA: AUTHOR [+2]

Abstract

Sigma-delta analog-to-digital converters require a digital filter to attenuate out of band components of the modulation that would otherwise be aliased into the useful signal band and to perform the required frequency decimation (typically, 128 to 1). The filtering task is greatly complicated by the fact that the input data rate is very high (10 MHz is typical).

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Fir Filter for Processing Sigma-Delta Modulator Outputs

       Sigma-delta analog-to-digital converters require a
digital filter to attenuate out of band components of the modulation
that would otherwise be aliased into the useful signal band and to
perform the required frequency decimation (typically, 128 to 1).  The
filtering task is greatly complicated by the fact that the input data
rate is very high (10 MHz is typical).

      This article describes an efficient means of performing the
digital processing of sigma-delta modulator outputs. The method
directly implements a multiplierless FIR filter which can perform the
complete digital signal processing task.

      There are two characteristics having to do with the nature of
sigma-delta modulators which greatly simplify the calculations needed
to implement a FIR filter.  The first is that the sigma-delta
modulator output signal is only a single line which can have only the
values of plus or minus 1 (representing plus or minus full scale).
This means FIR that no multiplications are required because all input
samples are either plus or minus one.  The multiplications can be
realized simply by adding or subtracting the filter coefficient
according to the sign of the input.  The second characteristic
peculiar to the sigma-delta method is that the data rate of the
output signal must be greatly reduced from the input data rate
(decimated by 128, for example). By simply not calculating the
samples which would otherwise be thrown away, it is possible to
perform the indicated computations with a reasonable number of time
shared adder circuits.

      Fig. 1 shows an example of a 2048-tap FIR filter decimated by
128/1 which requires 2048/128 or 16 additions per cycle.  The sigma-
delta modulator output determines the sign of each input.  The
addition steps must be repeated 128 times with a different set of
coefficients each time in order to complete the calculation.  The
final stage accumulates the total results over 128 cycles.

      Note that there are only sixteen possible outcomes at the
output of the second adder bank.  The filter is simplified by
pre-calculating these results and storing them as coefficients in the
coefficient RAM (or ROM).  This places the first two banks of adders.

      An implementation of the 2048-tap FIR filter using these
concepts is shown in Fig. 2.  Major elements of the design include
the data history RAM (a), the barrel shifter for processing the data
points (b), the coefficient storage RAM (c), and the arithmetic
section (d).  The pipelined architecture uses staging registers at
the RAM output, the adder tree, and the sum register (the output).
The pipeline operates at the clock rate of the input data.  One
output conversion is generated every...