Browse Prior Art Database

Fault-Secured Test Bus Architecture

IP.com Disclosure Number: IPCOM000102435D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 122K

Publishing Venue

IBM

Related People

Truong, KT: AUTHOR

Abstract

Disclosed is a state machine for Test Bus Architecture (TBA) design as proposed in the Joint Test Action Group (JTAG) to detect state transition error and to prevent corrupted test sequences. Since built-in test logic share the same environment with functional logic, it is very likely that unreliable test sequences could cause damages to the functional integrity of an untested chip on the same TBA interface. Therefore, the objective of fault-secured TBA is to provide a cost-effective method to detect and recover from this type of corrupted test sequence.

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Fault-Secured Test Bus Architecture

       Disclosed is a state machine for Test Bus Architecture
(TBA) design as proposed in the Joint Test Action Group (JTAG) to
detect state transition error and to prevent corrupted test
sequences.  Since built-in test logic share the same environment with
functional logic, it is very likely that unreliable test sequences
could cause damages to the functional integrity of an untested chip
on the same TBA interface.  Therefore, the objective of fault-secured
TBA is to provide a cost-effective method to detect and recover from
this type of corrupted test sequence.

      Proposed TBA standard in Fig. 1 required a four-wire interface:
           TDI : Test Data Input
           TMS : Test Mode Select
           TCK : Test Clock
           TDO : Test Data Output

      Fault-secured TBA adopted this standard with an error reporting
mechanism (ERR) for recovery.  It employs 2-out-of-5 coding to
provide adequate protection from state transition error.  Upon
detection, Error will be reported and the Instruction Register (IR)
will be forced to a non operative mode (NOP).  IR parity will also be
checked to deactivate the test outputs.  This dual action provides
the much needed fault-secure from corrupted test sequences.

      State assignments are designed to maximize totally self-test
capability by maximizing Hamming distance of the next state and the
present state.  The result is very attractive:

      RESET = '00011' = Power On Reset, reset instruction, recovery
state.
      IDLE = '0110' = Idle state wait for next operation.
      SELECT = '10001' = Intermediate state to select.
      LD_DR = '01010' = 'Active state', load data, check DR parity.
      LD_IR = '00110' = Ready to load instruction.
      START = '10100' = Start to shift.
      SHIFT = '01001' = 'Active state', shift data in DR or IR.
 STOP = '10010' = Stop from shifting, check DR or IR parity.
 PAUSE = '00101' = Waiting for tester or maintenance processor.
      EXEC = '11000' = If 'no error', then execute, else NOP.

      State assignments in conjunction with non-active recovery
sequences also provide...