Browse Prior Art Database

Phase-Transition Detector for Clock And Data Recovery

IP.com Disclosure Number: IPCOM000102439D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Soyuer, M: AUTHOR

Abstract

This article describes a new phase-transition detector (PTD) circuit for clock and data recovery from non-return-to-zero recording (NRZ) data. When used as a phase detector within a phase-locked loop (PLL), the proposed circuit also functions as a transition detector and a retime latch. The new PTD circuit centers the clock in the middle of the data eye opening and minimizes the jitter introduced during data transitions.

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Phase-Transition Detector for Clock And Data Recovery

       This article describes a new phase-transition detector
(PTD) circuit for clock and data recovery from non-return-to-zero
recording (NRZ) data.  When used as a phase detector within a
phase-locked loop (PLL), the proposed circuit also functions as a
transition detector and a retime latch.  The new PTD circuit centers
the clock in the middle of the data eye opening and minimizes the
jitter introduced during data transitions.

      Background PLL circuits are commonly used for clock extraction
from NRZ data.  A separate decision circuit is usually employed to
retime the data.  A nonlinear-processing stage can precede the PLL to
create the clock-frequency line or it can be inherent to the
phase-detector design.  This article describes a new phase-detector
scheme which falls into the second category and combines all three
functions mentioned above, i.e., nonlinear processing, clock recovery
and retiming or data recovery.  The main advantage of this design
over prior art is that the amount of jitter introduced by the
transition-gating process is minimized by providing an ideally zero
output voltage to the loop filter when the PLL is in lock.

      Circuit Description A PLL block diagram is shown in Fig. 1.
The loop contains a phase-transition detector (PTD), a loop filter
(LF), and a voltage-controlled oscillator (VCO).  The new PTD circuit
has three master-slave flip-flops, D1, D2 and D3, a NOR gate, N4, and
a half-bit time delay stage, DL5, as shown in Fig. 2.  The inputs to
the...