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Ground/VH Compensation for CMOS Boundary Scan Off-Chip Drivers

IP.com Disclosure Number: IPCOM000102445D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 95K

Publishing Venue

IBM

Related People

Bueck, F: AUTHOR [+6]

Abstract

A ground/VH shift, generated by transitions of switching off-chip drivers, yields a maximum permissible number of simultaneously switching devices (simultaneous switch rate). To maintain functionality, this simultaneous switch rate must not be exceeded by any chip.

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This is the abbreviated version, containing approximately 52% of the total text.

Ground/VH Compensation for CMOS Boundary Scan Off-Chip Drivers

       A ground/VH shift, generated by transitions of switching
off-chip drivers, yields a maximum permissible number of
simultaneously switching devices (simultaneous switch rate). To
maintain functionality, this simultaneous switch rate must not be
exceeded by any chip.

      If this rate is driven to its maximum for a quiet down-level
off-chip driver, the following failure mechanism becomes effective.

      During a high-to-low transition, the charge of the connected
load capacitance passes the N-device to GND.  In response to the
inductivity of the VH/GND supply to the chip, GND is shifted to VH.
This GND shift affects all devices on the chip.  If a quiet
down-level driver is subjected to GND shifting, a transient wave is
triggered from this driver.  Upon reaching the connected receiver/s,
this wave is reflected, doubling its magnitude.  The generated
voltage then switches the receiver/s to up-level, leading to
erroneously switching connected nets.

      The basic idea of this concept may best be described in terms
of standard wave theory: A wave "A" exposed to a wave "B" yields a
wave "C" by adding the amplitudes of the former two waves with regard
to their signs.  Applied to this case, the following condition has to
be met: Wave "A" produced by GND shifting is subjected to a new
device- generated wave "B" which at its optimum value equals the
inverted wave "A". The resultant wave "C" is a quiet line.

      The main device is a compensation capacitor Cc attached to a
full bridge of four FETs T1 to T4.  During the low master clock
-C_CLOCK', Cc is charged by T1 and T4, so that capacitor pole "I" is
positive and capacitor pole "II" is negative.  The rising master
clock edge turns off T1 and T4, isolating the charge of Cc.  In
response to a falling slave clock edge -N_B_CLOCK, the
compensator/decoder turns on T2 and T3 at the selected off-chip
drivers.  At this stage, some of the ...