Browse Prior Art Database

Electrical Performance Enhancement for Low-end Packaging

IP.com Disclosure Number: IPCOM000102452D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 5 page(s) / 171K

Publishing Venue

IBM

Related People

Snyder, CH: AUTHOR

Abstract

This article presents a simple method for reducing electrical noise due to lead inductance in low-end packaging. Such noise is often a limiting factor in low-end performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Electrical Performance Enhancement for Low-end Packaging

       This article presents a simple method for reducing
electrical noise due to lead inductance in low-end packaging.  Such
noise is often a limiting factor in low-end performance.

      For the purposes of this article, low-end packaging is
considered to be the combination of an electronic device mounted on a
first level package (TAB, PLCC, PFP, etc.) which is itself attached
to a second level package (circuit board, carrier, etc.).  The first
level package does not contain a ground plane; the second level
package may or may not contain a ground plane.

      One limit on the performance of low-end electronic systems is
inductive noise present on the power and ground leads of first level
packages.  This noise occurs during switching events and can disturb
the first level power and ground voltages, or can couple into nearby
signal leads, causing their signal levels to shift to erroneous
values. These conditions require that the amount of switching
activity be limited, that additional power and ground leads be
assigned, and/or that the placement of leads be restricted in order
to limit the noise.  Additionally, such noise can be radiated into
the environment as EMI.

      This article presents a simple modification to present second
level power and ground wiring such that the combined first and second
level wiring paths, when considered as an entity, exhibit a
substantial reduction in inductance and, consequently, in noise.
This improved performance can be obtained with negligible increase in
design, manufacturing, assembly or rework cost or degradation in
reliability or card wireability.  This method can be applied to
present or future products containing first level packages without
ground planes.

      To illustrate the concept disclosed here, consider Fig. 1(a),
which shows a TAB device mounted on a second level carrier.  A ground
lead from the chip to the carrier is shown on the right.  In
conventional second level wiring methods, the ground lead to ground
plane connection is made by wiring out away from the TAB to a via
which connects to a ground plane, as shown.  Generally, a line drawn
along the first level lead will also fall along the second level
wiring, so that the lead and associated wiring form one linear
conductor.

      Although the inductance from the chip to the power plane could
be minimized by placing a via directly in the pad where the lead is
bonded to the second level carrier, frequently the wiring pattern for
the first level package is defined prior to the assignment of power
and ground leads. These patterns are sometimes developed and stored
for use anytime a matching first level package needs to be wired, so
they are developed to allow wiring out all of the leads, and do not
address whether any particular lead is a signal lead or a power or
ground level.

      When the lead, wiring and via inductances of the conventio...