Browse Prior Art Database

Exclusive OR Circuits

IP.com Disclosure Number: IPCOM000102455D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Coppens, P: AUTHOR [+4]

Abstract

Circuit designs of a two-way exclusive OR (XOR2) and a two-way exclusive NOR (XNOR2) functions and extensions thereof are disclosed below.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 96% of the total text.

Exclusive OR Circuits

       Circuit designs of a two-way exclusive OR (XOR2) and a
two-way exclusive NOR (XNOR2) functions and extensions thereof are
disclosed below.

      The design of the two-way exclusive OR is proposed in CMOS
technology. The circuit schematic shown in Fig. 1 is based on the
usage of full transfer gates. Devices Tn1-2-3-5 and devices Tp1-2-3-5
implement the logical XNOR function, and devices Tn4 and Tp4 invert
the XNOR to deliver the XOR function, give the high output drive
capability, and finally buffer the inputs from the output load.
 The worst-case delay is 1.8 ns for a standard CMOS technology.

      Note that in a typical design, the complement value of a signal
are already generated, within the logic; in this case, the inversion
of B0 can be eliminated.

      Similarly, by interchanging the Tn2-3 and Tp2-3 devices, the
circuit becomes a two-way exclusive NOR (XNOR2).

      The above-proposed circuits, XOR2 and XNOR2, exhibit,
respectively, over 35% and 40% advantage in delay, while requiring
20% less transistors than the current state-of-the-art XOR2 circuits.
The family can even be extended to a three-way Exclusive OR (XOR3),
as shown in Fig.  2.

      The circuit of Fig. 2 requires less transistors than present
state-of-the-art design, improving its density by up to 40%.

      Finally, based on the same technique as above, the circuit of
Fig.  2 can be modified to perform a three-way Exclusive-OR NOT
(XOR...