Browse Prior Art Database

Method of Stopping a Clock Signal Without Additional Skew

IP.com Disclosure Number: IPCOM000102461D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 34K

Publishing Venue

IBM

Related People

Knauft, G: AUTHOR [+3]

Abstract

The clock signals must be independently stoppable for a system to function properly.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Method of Stopping a Clock Signal Without Additional Skew

       The clock signals must be independently stoppable for a
system to function properly.

      For this purpose, the clock path is provided with an additional
gate ensuring an inactive level at the driver input.  As there are
both positively and negatively active clocks, that gate is an AND- or
an OR- circuit.  AND- and OR-circuits have different basic delays
leading to increased skew between the individual clocks.

      The method described below eliminates the additional gate in
the clock path by using a driver with a boundary scan latch which is
normally provided exclusively for testing.  Regardless of the control
input, the output signal of this driver is either the signal applied
to the driver input or the contents of the boundary scan latch.

      To ensure that the circuit functions properly, the boundary
scan latch is set in accordance with the inactive level of the clock
signal.  For stopping the clock signal, the control input of the
driver is switched, so that the clock signal at the input of the
driver no longer determines the output signal.

      This method has the advantage that there is no additional skew
and that the polarity of the control line is uniform, meaning that
the same signal may be used to stop positively and negatively active
clock signals.