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Browse Prior Art Database

High Performance Dram Data Buffer

IP.com Disclosure Number: IPCOM000102463D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 138K

Publishing Venue

IBM

Related People

Ganser, DD: AUTHOR [+3]

Abstract

Described is a high speed data buffer that improved DMA performance by using the page-mode feature of Dynamic RAM (DRAM), reducing the number of read-modify-write cycles to memory and by buffering the DMA data in a high performance RAM. The high performance data buffer was implemented as an imbedded RAM array within a VLSI memory controller. The high performance data buffer significantly reduced the DRAM utilization of DMAs by reading or writing the data to the DRAM arrays as fast as possible. On DMA read operations, page-mode was used to quickly read the data from memory into the data buffer where it later would be available for the slower DMA read operations. On DMA write operations the data buffer was loaded by the slower DMA write operations and then quickly unloaded to memory using page-mode.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

High Performance Dram Data Buffer

       Described is a high speed data buffer that improved DMA
performance by using the page-mode feature of Dynamic RAM (DRAM),
reducing the number of read-modify-write cycles to memory and by
buffering the DMA data in a high performance RAM.  The high
performance data buffer was implemented as an imbedded RAM array
within a VLSI memory controller.  The high performance data buffer
significantly reduced the DRAM utilization of DMAs by reading or
writing the data to the DRAM arrays as fast as possible.  On DMA read
operations, page-mode was used to quickly read the data from memory
into the data buffer where it later would be available for the slower
DMA read operations.  On DMA write operations the data buffer was
loaded by the slower DMA write operations and then quickly unloaded
to memory using page-mode.

      The figure illustrates a block diagram of the high speed data
buffer.  The data buffer is a 2-port imbedded RAM array consisting of
n locations of m-bytes each.  This RAM supports concurrent read or
write accesses on both ports. The following support logic is also
needed for the data buffer:
-  DBAREG - Data buffer address register is a counter used to hold
the RAS/CAS address for the next memory access.  The DBAREG is loaded
with the starting address of every DMA.  The DBAREG is then
incremented after each time CAS is asserted and the column address
hold time is met.
-  DBUREG - Data buffer usage register is a bit register that is
updated whenever new data is written to the data buffer. This
register is used to indicate what data byte locations in the data
buffer hold valid data.
-  DBCREG - Data buffer control register is used to select the DMA
controllers that are enabled for using the data buffer. Since the DMA
bus arbitration was handled in the memory controller, the device
controlling the DMA bus at any time was known. Some DMA controllers
only had the capability to transfer one or two bytes of data during a
DMA.  For these devices it would be inefficient to use the data
buffer.  So, it was best to bypass the data buffer in these cases and
DMA the data directly to or from DRAM. A separate bit in the DBCREG
is provided for each DMA device.
-  RAM address counters 1 and 2 are used to address the next m-byte
element being accessed on each side of the 2-port RAM. The RAM
address counters are zeroed at the beginning of every DMA.

      DMA Reads from DRAM using the Data Buffer:  On DMA reads, the
data buffer must be first loaded with data from the DRAM.  This is
done by reading the DRAM in page-mode by first presenting the row
address for the page of memory being accessed and then asserting row
address select (RAS). The memory controller then asserts the column
address and column address select (CAS) for each DRAM location read
in page-mode.  After going through ECC correction logic the data from
DRAM is stored into the first four bytes of the data buffer.  This
da...