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Circuitry for Detecting Clock-Stop Situations

IP.com Disclosure Number: IPCOM000102476D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Hilgendorf, RB: AUTHOR

Abstract

This article describes circuitry for detecting clock-stop situations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Circuitry for Detecting Clock-Stop Situations

       This article describes circuitry for detecting clock-stop
situations.

      IBM systems use both stoppable and continuously running clocks.
For parts of such systems working with the continuous clock it may be
necessary to know the state of the stoppable clock.  This information
is provided as a separate signal by clock generation circuitry.  In
some cases where such a signal is unobtainable, the circuitry
described below is used to detect clock-stop situations in situ.

      The circuitry consists of two latches and a comparator. One of
the latches is clocked by the continuously running clock, and the
other by the stoppable clock.  The inverted output of the latch
clocked by the stoppable clock is used as an input for both latches
in parallel, so that with each clock cycle, both latches change their
state in parallel. This way both latches have identical outputs, and
the comparator will be "equal".  If one clock stops, the other latch
will change to the inverted state of the stopped latch, retaining
that state until the clock restarts.  In this case, the comparator
will be "not equal".  As a result, the comparator output supplies the
clock-stop signal directly.