Browse Prior Art Database

High Speed Multiply Using a 5-Way Adder

IP.com Disclosure Number: IPCOM000102482D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

Maass, KK: AUTHOR [+2]

Abstract

Disclosed is a logic design to generate the partial product in a fixed-point High Speed Multiply, on one chip, using a 5-way adder followed by a CPA (carry propagate adder). The sum output of the CPA is the partial product and is latched up in a register.

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High Speed Multiply Using a 5-Way Adder

       Disclosed is a logic design to generate the partial
product in a fixed-point High Speed Multiply, on one chip, using a
5-way adder followed by a CPA (carry propagate adder).  The sum
output of the CPA is the partial product and is latched up in a
register.

      A conventional fixed-point multiplier can retire 8 multiplier
bits per machine cycle.  The rightmost 8 multiplier bits of the
32-bit multiplier that originate from the GPRs (general purpose
registers) are decoded in the first cycle.  The eight multiplier
bits, decoded in four groups of 3 bits, each group overlapping
another by one bit, generate 3 gate lines for each of the four groups
100 (Fig. 1).  This decode scheme is a modified Booth algorithm which
was described earlier [*].

      One gate line of each of the four groups modifies the
multiplicand (101 in Fig. 1).  The four modified multiplicands and
the partial product shifted right 8 from the previous cycle are added
together in 3-2 reduction adders 102 to form a sum and carry.  The
resulting sums and carrys are latched (103) (40 sum latches and 40
carry latches) and represent the partial product.  On the next cycle
the rotator 104 shifts the multiplier right 8 so that the next 8 bits
can be decoded.  Four modified multiplicands and the previous cycle
partial product shifted right eight (which was stored in carry
latches and sum latches 103) are added in CSA adders 102 and the
result latched.

      The right 8 shifted bits of carry and sum that did not
participate in the addition through the CSA adders are added in a CPA
106.  The resulting 8-bit sum is latched in an accumulating register
105 that holds the final product.  The final product is accumulated,
a byte per cycle in register 105.  On the fifth cycle, the final
product byte from the CPU is concatenated with the 3 bytes from
register 105 and sent to the G...