Browse Prior Art Database

Multiple Phase Clock Generation From a Single Oscillator

IP.com Disclosure Number: IPCOM000102485D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Grosbach, LE: AUTHOR [+3]

Abstract

Disclosed is a low cost, high accuracy method for providing multiple clock edges in a single system cycle. It is low cost because an oscillator is the only required off-chip component. It is accurate because the oscillator edges are the critical path through the clock generation and only pass through two levels of circuits. Also, only two I/Os per chip are required, one for the oscillator input and one for the synch pulse. In addition, the timing requirement for the chip crossing of the synch path has been increased to half of the system cycle, making it a relatively easy timing to meet. By using higher frequency oscillator inputs, this technique is extendable to more than four edges per cycle. It is only limited by the minimum pulse-width capability of the chip it is implemented on.

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Multiple Phase Clock Generation From a Single Oscillator

       Disclosed is a low cost, high accuracy method for
providing multiple clock edges in a single system cycle.  It is low
cost because an oscillator is the only required off-chip component.
It is accurate because the oscillator edges are the critical path
through the clock generation and only pass through two levels of
circuits.  Also, only two I/Os per chip are required, one for the
oscillator input and one for the synch pulse.  In addition, the
timing requirement for the chip crossing of the synch path has been
increased to half of the system cycle, making it a relatively easy
timing to meet. By using higher frequency oscillator inputs, this
technique is extendable to more than four edges per cycle.  It is
only limited by the minimum pulse-width capability of the chip it is
implemented on.

      By using an oscillator of the desired cycle time, which is a
frequency multiple of 2, 4, etc., we can get as many accurate edges
as the logic technology will allow based on its minimum pulse-width
passing capability.  The trick is to force the oscillator input to be
the critical path through the clock generation.  This is accomplished
by gene rating selector pulses which completely encapsulate selected
oscillator pulses (see Fig. 3).  That way the oscillator edges
actually control the delay tolerance, not the counter which is
generating the selector pulses.  By avoiding the delay of the counter
as the cr...