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Data-Out Restore Circuit Improving Access Time of Memory Arrays

IP.com Disclosure Number: IPCOM000102493D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+3]

Abstract

This article describes a circuit which improves the access time of CMOS memories. In a very simple and cheap manner it anticipates the data output swing during the restore of the output latch.

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This is the abbreviated version, containing approximately 80% of the total text.

Data-Out Restore Circuit Improving Access Time of Memory Arrays

       This article describes a circuit which improves the
access time of CMOS memories. In a very simple and cheap manner it
anticipates the data output swing during the restore of the output
latch.

      The voltage difference (WV) developed during a Read access by
the selected cell connected to the Bit Line pairs is applied to a
Sense Amplifier (first stage) and then to an output latch (second
stage). The major problem is for the first stage to quickly amplify
the created WV. This is why this stage is restored high in a floating
mode, then connected to ground when the WV is sufficient (DLR and
SET1 signals in Fig. 1).

      The second stage with a higher gain is also restored high and
set when WV developed by the first stage is large enough (L1R and
SET2 signals in Fig. 1).

      During the restore of the second stage the Data Out level (DO)
goes normally to ground, following the restore. Two possibilities
arise (Fig. 2):
     - READ 0 : DO stays at 0
     - READ 1 : DO goes high in a full swing transition.

      It is during the restore that the new circuit breaks in the
operation. Instead of having DO fully swinging to ground, a slight
modification of the output driver (2-way NAND instead of a standard
driver) stops the falling down of DO in an intermediate state, thanks
to the latch restore signal (L1R). Then the Read output occurs
(Fig.3):
     - READ 0 : DO resumes i...