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Improved Planarization Scheme for Deep Trench Isolation

IP.com Disclosure Number: IPCOM000102500D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Chen, TC: AUTHOR [+4]

Abstract

Disclosed is a process for reducing deviations from planarity associated with the deep trench process. Two chem-mech polish steps are used, allowing a very high degree of planarity to be achieved as described below. The achievement of a planar surface becomes increasingly important as lateral device dimensions are scaled into the sub-micron regime and as new device structures are explored (for example, structures with one or more junctions butted to the deep trench).

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Improved Planarization Scheme for Deep Trench Isolation

       Disclosed is a process for reducing deviations from
planarity associated with the deep trench process.  Two chem-mech
polish steps are used, allowing a very high degree of planarity to be
achieved as described below.  The achievement of a planar surface
becomes increasingly important as lateral device dimensions are
scaled into the sub-micron regime and as new device structures are
explored (for example, structures with one or more junctions butted
to the deep trench).

      Current art (polysilicon refilled deep trench) involves removal
of the excess polysilicon from the deep trench fill by a chem-mech
polish process, leaving the structure shown in Fig. 1a.  The level of
the polysilicon fill in the deep trench ("h" in Fig. 1a) will, in
general, vary significantly across a given wafer and from wafer to
wafer depending on such variables as the amount of overpolish, the
amount of field oxide removed during the chem-mech polish, and the
local density (i.e., pattern factor) of the deep trenches. This
non-uniformity translates directly into a variable non-planarity in
the final structure.  To avoid this problem, the following solution
is proposed.  A field dielectric consisting of separate nitride and
oxide layers is used as shown in Fig. 1b.  After the chem-mech polish
to remove the excess polysilicon from the deep refill, the oxide is
removed by means of an HF etch.  This leaves the polysilicon
pro...