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Browse Prior Art Database

High Speed Bicmos "XOR 3" Circuit

IP.com Disclosure Number: IPCOM000102509D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR

Abstract

The speed of a digital circuit like an array MULTIPLIER or an ADDER is a function of the basic speed of the full sum calculation made on 3 bits. Such a function is usually implemented in XOR 3 inputs. A XOR 3 can be made with 2 XOR or XOR-NOT in series, which leads to the longest delay. Several types of integrated XOR 3 way have been proposed (1,2). For comparison with the new proposed scheme a fast conventional XOR 3 (1) implemented with pass NFET and PFET transistors is shown in Fig. 1. In this scheme, the inputs are made at the sources of the input transistors. One of the problems of such a circuit is its use in an ASIC, where the delay must be predetermined before the prototype realization. With pass gates the delay and the load seen from the previous stage are a function of the state of the other inputs.

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High Speed Bicmos "XOR 3" Circuit

       The speed of a digital circuit like an array MULTIPLIER
or an ADDER is a function of the basic speed of the full sum
calculation made on 3 bits. Such a function is usually implemented in
XOR 3 inputs. A XOR 3 can be made with 2 XOR or XOR-NOT in
series, which leads to the longest delay. Several types of integrated
XOR 3 way have been proposed (1,2).  For comparison with the new
proposed scheme a fast conventional XOR 3 (1) implemented with pass
NFET and PFET transistors is shown in Fig. 1.  In this scheme, the
inputs are made at the sources of the input transistors. One of the
problems of such a circuit is its use in an ASIC, where the delay
must be predetermined before the prototype realization.  With pass
gates the delay and the load seen from the previous stage are a
function of the state of the other inputs. The delay is thus very
difficult to predict when compared to traditional CMOS where all
loads are capacitance only.

      The new BiCMOS XOR 3 proposed in Fig. 2 is a high speed XOR
which uses pass gates not at the input but after a first CMOS
inverter. For all the inputs both phases are used. The delay for this
circuit is reduced if both phases are already available from the
previous stages.  The XOR and the XOR-NOT functions of inputs A0 and
A1 are generated in parallel. They are connected to the FET gates of
the final XOR to reduce the delay. The in-phase and out-of-phase of
the third signal A2 is connected t...