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Browse Prior Art Database

Pulsed Restore for CMOS DRAM Sensing Clocks

IP.com Disclosure Number: IPCOM000102516D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Katayama, Y: AUTHOR [+2]

Abstract

Pulsed restore circuitry for CMOS DRAM sensing clocks SLN and SLP, which avoids the full restore of the two clocks to the equalization level in order to reduce the noise in the slow slope sensing period and provide stable operation in spite of process deviations, is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 82% of the total text.

Pulsed Restore for CMOS DRAM Sensing Clocks

       Pulsed restore circuitry for CMOS DRAM sensing clocks SLN
and SLP, which avoids the full restore of the two clocks to the
equalization level in order to reduce the noise in the slow slope
sensing period and provide stable operation in spite of process
deviations, is disclosed.

      A special narrow pulse restores the SLN and SLP lines to a
sufficient extent to avoid any unplanned activation of the sense
amplifiers even if noise is present but does not restore them to the
equalization level.

      The figure shows the pulsed restore circuit with a typical
column of a DRAM array.  The input signal PEQ is the clock which
starts the equalization in the array.  PMOS devices turned on by this
PEQ clock short the bit lines together and connect them to VEQ, which
is an intermediate voltage level.  In the proposed circuitry, the
inverter delay chain and edge detection circuitry shown in the figure
generate a pulsed clock whose leading edge is delayed from PEQ by
inverter chain 1 and has a pulse width which is determined by the
delay chain 2. The array equalization starts earlier that SLN and SLP
equalization so SLN and SLP are restored to a certain extent through
the sense amplifier's cross-coupled devices in the column. When the
pulse P occurs, SLN and SLP are partially shorted together. The final
voltage of SLN and SLP are determined by the shorting device size and
parasitic capacitance of SLN and SLP.

     ...