Browse Prior Art Database

Computer System Channel Performance Enhancement Via Address Boundary Release

IP.com Disclosure Number: IPCOM000102532D
Original Publication Date: 1990-Nov-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 46K

Publishing Venue

IBM

Related People

Keener, DS: AUTHOR [+4]

Abstract

This article describes a technique for use in a computer system which allows for optimization of data transfer across the system channel from a bus master to a "paged" memory controller by synchronizing the data transfer start and stop addresses to those that are optimal for the particular paged memory controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Computer System Channel Performance Enhancement Via Address Boundary Release

       This article describes a technique for use in a computer
system which allows for optimization of data transfer across the
system channel from a bus master to a "paged" memory controller by
synchronizing the data transfer start and stop addresses to those
that are optimal for the particular paged memory controller.

      Many computing systems have a "paged" type memory system where
a bus master on the system channel communicates indirectly with main
memory through a memory control mechanism.  This memory control
mechanism fetches a page of memory from main memory at very high
speed and then dispenses the information to the system channel at
lower speeds.  This allows decoupling of a slow speed IO device from
the high-speed memory and processor, thus allowing higher system
throughput due to non-interference.  If the memory controller senses
an impending page boundary crossing, then it will prefetch the next
page.  However, if a bus master crosses over the page boundary
(accesses a byte in the next page) before the next page is loaded,
the memory controller must place wait states in the transfer while
the next page is fetched.  This holds up the bus in an idle state.
The technique disclosed herein prevents this holdup.

      The problem occurs because current bus masters do not consider
the address of the data to be transferred in determining when to
release the bus.  The...