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High-Speed Logic to Implement Byte Addition Without Impacting the Performance Associated With the Addition of Half- Or Full-word Entities

IP.com Disclosure Number: IPCOM000102553D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR

Abstract

Described are a method and circuit arrangement which optimize the performance of a half- or full-word adder, while allowing for the implementation of byte and/or half-word addition using the primary or principal carry-in at the respective boundary or boundaries of the main adder circuit.

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High-Speed Logic to Implement Byte Addition Without Impacting the Performance Associated With the Addition of Half- Or Full-word Entities

       Described are a method and circuit arrangement which
optimize the performance of a half- or full-word adder, while
allowing for the implementation of byte and/or half-word addition
using the primary or principal carry-in at the respective boundary or
boundaries of the main adder circuit.

      Fig. 1 shows a circuit schematic for implementing the byte
addition capability.  The schematic shows a carry select 16-bit adder
with integrated byte add capabilities. The final sum generation is
omitted for clarity.  The first 10 bits are implemented using a 4-bit
unit in conjunction with a 6-bit unit.  The remaining 6 bits required
to implement the half-word adder are realized by essentially
duplicating the previous 6-bit entity.

      In order to access the 8-bit boundary where the primary
carry-in signal must be multiplexed with the 8-bit carry-out, an
additional 2- bit carry generation unit is implemented.  The carry
outputs of the carry generation units associated with the 10th
physical bit (logical bit #6), CO6(0) and CO6(1), and the carry
output of the additional 2- bit carry generation unit, COBYTE are
supplied to a decoder/selector in conjunction with the respective
control signals, CO12T, CO12C and BYTE.  The outputs of this circuit
are supplied to the final carry selector for the half-word adder.
Fig. 2 illustrates the circuitry used to implement the 2-bit carry
generator bypass and associated decoder/ selector.

      The operation can be described as follows; the primary carry-in
is supplied as the carry-in to the 2-bit carry generate circuit.  The
partial sums and partial sum complements associated with the 9th and
10th physical bits (logical bits 7 and 6, respectively), are provided
as the controls, the same as is done for the normal carry generate
circuitry.  The controls either steer the primary carry-in to the
output of this 2-bit carry generate circuit or allow the creation of
the appropriate value based on the data values for logical bits 7 and
6.  When the BYTE control line is active, the carry out of the 2-bit
carry generate bypass circuit is steered to the decode...