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Three Modes of Chip Operation Selectable From a Single Pad-To-Pin Connection Option

IP.com Disclosure Number: IPCOM000102556D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Hiltebeitel, N: AUTHOR [+2]

Abstract

By selecting one of three pad-to-pin connection options: 1) pad to external high voltage supply (Vcc), 2) pad to ground (Vss), or 3) pad left open, an on-chip circuit is activated to operate a dynamic random- access memory (DRAM) chip in one of three different modes. One on-chip circuit is described which produces a signal at one of three output ports by selecting one of the three connection options.

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Three Modes of Chip Operation Selectable From a Single Pad-To-Pin Connection Option

       By selecting one of three pad-to-pin connection options:
1) pad to external high voltage supply (Vcc), 2) pad to ground (Vss),
or 3) pad left open, an on-chip circuit is activated to operate a
dynamic random- access memory (DRAM) chip in one of three different
modes.  One on-chip circuit is described which produces a signal at
one of three output ports by selecting one of the three connection
options.

      Referring to the figure, Vcc for this example is 5.0 volts,
internal regulated supply Q is 3.6 volts.  N-type transistors T8 and
T9 are long channel devices which limit current and set up a 1.2 volt
reference at node N5 when node S rises.

      Transistor T12 holds stress low on T11 when node S is low and
pad P is bonded to Vcc.  Transistors T11 and T12 are long channel
devices to limit current.  Transistor T10 holds stress low on
transistors T1 and T6.

      After chip power-up and rise of mode input M, through inverter
I1, node LP falls, thus powering down P devices in latches L1 and L2.
Node S rises, allowing latch inputs through transistors T0, T2, T3,
and T4 to be sensed.  When input M falls and node LP rises, signal
inputs to latches L1 and L2 are sensed.  Then, node S falls which
isolates latches L1 and L2 from the inputs.

      If pad P is connected to Vcc and input M rises, transistors T11
and T12 are off and node N6 rises to a voltage V = Vc...