Browse Prior Art Database

New Design of the Terminal Via Mask

IP.com Disclosure Number: IPCOM000102557D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 117K

Publishing Venue

IBM

Related People

Guillot, A: AUTHOR [+3]

Abstract

Disclosed is a terminal via mask with the following modifications: * No wide terminal polyimide surface close to the chip. * Kerf all around the chips at the wafer rim. * Polyimide remained at the wafer rim where there are no chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 90% of the total text.

New Design of the Terminal Via Mask

       Disclosed is a terminal via mask with the following
modifications:
      * No wide terminal polyimide surface close to the chip.
      * Kerf all around the chips at the wafer rim.
      * Polyimide remained at the wafer rim where there are no chips.

      The goal is to avoid chips with edge seal at the rim of the
wafers (terminal polyimide from the chip to the kerf as shown in the
figure).

      During polyimide coating, a polyimide build-up is often created
at the wafer rim. Consequently, in this zone, the polyimide is not
etched enough depending on the chip position and on the polyimide
build-up.  The percentage of defective chips is not negligible.

      On the other hand, the chips are out of specifications, if
metal bubbling occurs. In this area, the polyimide thickness is
increased and the differential etching between the chip and the kerf,
is not selective enough to have chips within the specifications (see
the figure).

      The terminal via mask is so modified to avoid small trenches to
be etched between the chip and the kerf or between the chips and the
wafer rim.

      As a consequence, the wide polyimide surface is more easily
removed and, therefore, chips are within the specifications. On the
other hand, where metal bubbling occurs, the chip is less sensitive
to the edge seal defects.

      With this new design, the bad chips per wafer according to the
edge seal para...