Browse Prior Art Database

Fast Memory Address Test for IPL ROS

IP.com Disclosure Number: IPCOM000102576D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+4]

Abstract

Disclosed is a fast method to detect address errors in system memory. The address test presented in this disclosure does not require accessing all of the memory to test for address errors as in some other address tests. Only a small fraction of the memory is referenced. This is accomplished by strategically picking addresses that will catch any address line problems and referencing only these addresses during the test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fast Memory Address Test for IPL ROS

       Disclosed is a fast method to detect address errors in
system memory.  The address test presented in this disclosure does
not require accessing all of the memory to test for address errors as
in some other address tests. Only a small fraction of the memory is
referenced.  This is accomplished by strategically picking addresses
that will catch any address line problems and referencing only these
addresses during the test.

      In the system that we developed this test for (IBM RISC
System/6000* 530, 730, 930), the real address is a 32-bit address and
a data word is 32 bits wide.  Of the 32 address bits, only address
bits A4-A27 are used to generate the row/column address which is what
this address test tests. Of the remaining address bits, A0-A3 are
used to select the memory bank while A28-A31 are not used to address
the data on the memory card because the memory bus is a quad-word (4
words) wide.  The processor also has a diagnostic I/O to read and
write both data and ECC bits.  These I/Os are 20-word string ops with
16 words of data and 4 words of ECC bits.  The test procedure is
described below.
      1.   Store 20 words (16 data words and 4 ECC words) of
           '00000000'x to address '00000000'x.
      2.   Load 20 words from address 0 and save the 20 words
           in the cache.  This is to account for possible
           data stuck bits or floating bits.
      3.   Store 20 words of 'FFFFFFFF'x to the following
           addresses base address of the bank and up to the
           base address of the bank + bank size.
              '00000040'x      '00002000'x       '00100000'x
              '00000080'x      '00004000'x       '00200000'x
              '00000100'x      '00008000'x       '00400000'x
              '00000200'x      '00010000'x       '00800000'x
              '00000400'x      '00020000'x       '01000000'x
              '00000800'x      '00040000'x       '02000000'x
              '00001000'x      '00080000'x       '04000000'x
                                                 '08000000'x
      4.   Load from address 0 and confirm that the original
           values at address 0 are unchanged.  If not, then
           there is an address problem.
     ...