Browse Prior Art Database

Fast Algorithm for Most Efficient Bit-Steering

IP.com Disclosure Number: IPCOM000102579D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 7 page(s) / 211K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+3]

Abstract

This bit-steering algorithm was developed to to maximize the number of good blocks of memory after bit-steering is completed. This method was developed to use information gathered during data testing. This reduces the need to perform similar data tests more than once. Therefore, this test will not take much longer to run than a data-only test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Fast Algorithm for Most Efficient Bit-Steering

       This bit-steering algorithm was developed to to maximize
the number of good blocks of memory after bit-steering is completed.
This method was developed to use information gathered during data
testing.  This reduces the need to perform similar data tests more
than once. Therefore, this test will not take much longer to run than
a data-only test.

      This algorithm was developed for a system with the following
hardware features:
  - The system can have 1-16 banks of memory.
  - An ECC word is 40 bits:  32 data bits, 7 check bits, and 1
spare bit.
  - It is the spare bit that is 'bit-steered' to replace a faulty bit
in one of the other 39 locations of the ECC word.
  - A spare bit from 1 ECC word cannot be steered into another ECC
word.
  - The memory bus is 4 ECC words wide.  Each bank has 4 groups of
ECC words.
  - Each bank of memory can be bit-steered independently of any other
bank.  Each group of ECC words can be bit-steered independently of
any other.
  - Within each bank, 1 bit can be bit-steered per ECC word.
  - The length of loads and stores is a cache line, which is 128
bytes or 8 memory bus transfers.
  - There is a test mode that writes data bit 0 into the spare bit
and compares the spare bit to data bit 0 during reads.  In this test
mode, if data bit 0 does not match the spare bit then an error will
be flagged.  This mode is called XOR/D0 because an error is indicated
by the XOR of the spare bit and data bit 0.
  - For read ECC error reporting, the following modes are selectable:
     - Test mode for spare bit (XOR/D0):  ON/OFF
     - Interrupts on errors:  ON/OFF
     - Data correction:  ON/OFF
  - Syndromes can be stored in an error register when one-bit-errors
(1BE) occur.

      Fig. 1a shows the relationship between Banks, ECC words, and
Blocks.  Fig. 1b indicates the independent bit-steering groups for 2
banks of memory.  Fig. 1c shows one of the sixteen Bit-Steering
Configuration Registers (BSCRs).

      The following are the requirements of the bit-steering/memory
test code:
  - The memory is divided into 16k blocks that can be deallocated
(marked bad).
  - If a block of memory cannot be corrected completely with
bit-steering, then it is marked bad.
  - After bit-steering/memory test is complete all blocks of memory
that are not marked bad should have correct ECC in the check bits.
  - The bit-steering/memory test should be as fast as possible.
  - The maximum number of 16k blocks should be saved with bit
steering.

      In this method bit-steering can be done on the bank of memory
after the data test has been completed and bit steering should be
done based on the information obtained by the data test.  Also,
blocks that still have bad bits after bit-steering will be marked
bad.  Before this procedure starts, an area of memory is found that
has no errors.  That good area of memory is used for the bad b...